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KP100 Japan MOL validation standard mask in Austria

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CMOS MEMSAdvanced Micro and Nanosystems PDF Free

The hard mask typically consists of a PECVD silicon nitride layer, if necessary with a pad of oxide underneath. Care must be taken to minimize the pinhole density for the subsequent anisotropic wet etching step. The etch mask is patterned using a double side mask aligner, aligning the patterns on the wafer back to front side structures.

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